3-D spiral stacked inductor on semiconductor material

ABSTRACT

A parallel spiral stacked inductor and manufacturing method therefore is provided. A substrate has a plurality of turns in a plurality of levels, the plurality of turns having a center proximate and a center distal ends. A first plurality of vias connecting the center proximate ends of the plurality of turns and a second plurality of vias connecting the center distal ends of the plurality of turns. A first connecting portion connects to the center proximate ends of the plurality of turns and a second connecting portion connecting to the center distal end of the plurality of turns. A dielectric material contains the inductor.

TECHNICAL FIELD

[0001] The present invention relates generally to integrated circuitsand more particularly to on-chip silicon-based inductors.

BACKGROUND OF THE INVENTION

[0002] Increasing demands for personal mobile communications equipmenthave motivated recent research activities to focus on the development ofinexpensive, small size, low power consumption, and low noise levelsystems. To satisfy these requirements, one of the most important andindispensable circuit components is the on-chip silicon-based inductor.

[0003] As a result, miniaturization of the inductor on silicon hasbecome a current key research area and extensive work has been done inthis area. However, despite efforts by many researchers having skill inthe art, achieving high performance on-chip inductors, i.e., highqualify factor (Q), still remains a major problem especially when radiofrequency integrated circuits (RFICs) are built on silicon.

[0004] Conventional inductors built on silicon are generally planar innature. The current complementary metal oxide semiconductor (CMOS)process uses a very conductive substrate. Spiral inductors fabricated onsuch a lossy substrate suffer from high capacitive and magnetic losses.

[0005] In addition, high dynamic resistance of metal lines at GHzfrequency ranges further degrades the inductor performance in CMOStechnology as compared to those fabricated in monolithic microwaveintegrated circuits (MMICs).

[0006] Many fabricating techniques, processes, and materials have beenproposed to improve the performance of on-chip inductors. Tediousprocessing techniques such as etching away the silicon substrate underthe inductor have been introduced to remove the substrate parasiticeffects completely. Despite achieving good results, industries arereluctant to adopt such a technique because of reliability issues suchas packaging yield, as well as long-term mechanical stability.

[0007] Another approach to minimize the substrate loss for silicon-basedinductors has been to increase the substrate resistivity. This techniquehas yielded significant results, however, the substrate becomesunsuitable for building active MOS devices.

[0008] The most critical factor hindering the performance ofsilicon-based inductors is the high resistive aluminum-copper (AlCu)interconnects used in silicon processes.

[0009] In comparison, thicker and less resistive gold (Au) metalizationtogether with lossless substrate in gallium arsenide (GaAs) technologypermits high performance inductors to be fabricated easily. To overcomehigh metalization resistance, a popular technique is to have the layersof metal stacked together, thereby achieving a high Q inductor.

[0010] Another possible alternative is to use an active inductor. In anactive inductor high Q factor and inductance can be achieved in a reallysmall silicon area. However, such approach suffers from high powerconsumption and high noise levels that are not acceptable for low powerand high frequency applications. In addition, performance of activeinductors are very sensitive and dependent upon the inductor's biasingcircuitry, making it time consuming and tedious to design.

[0011] As a result of the above, the simplest and most commonly usedon-chip inductors are planar silicon-based spiral inductors, whichrequire careful layout optimization techniques to improve performance.

[0012] In the conventional spiral inductor design, the inductor isplanar and fabricated on a conductive silicon substrate. To improve theQ factor of the spiral inductors, the top metal is usually stacked witha few layers of lower metal through vias to minimize the overall metalseries resistance. Nevertheless, when more layers are used to realize avery thick conductor, the whole spiral is brought closer to thesubstrate. This increases the spiral-to-substrate parasitic capacitanceand hence results in a degradation of Q factor as well as the inductor'sself-resonant frequency. Nevertheless, improvement and quality factorsare still observed for a 4-layer stacked inductor at 2.45 gigahertz(GHz).

[0013] The above technique to improve the inductor's quality factor iswell known and very popular in the industry since it involves nomodification to the existing CMOS process flow. Currently, parallelinductors have never been explored because those skilled in the artexpect the performance of such parallel inductors to be very poor. For a2-metal-layer parallel inductor, its conductor parasitic resistance,especially high dynamic resistance at gigahertz frequencies willdecrease by 50%. This helps improve the inductor's Q factor but itsresultant inductance will also be lower by 50%. In typical planarparallel inductors, the advantage over the conventional spiral inductoris that vias required for the underpass center conductor connection canbe omitted and this greatly reduces the conductor's series resistance;i.e., the inductors are planar, open, concentric rings which arecommonly connected at their open ends. Comparing the inductance and Qfactor of a conventional circular inductor (3-turn) and a planarparallel inductor, it was observed that by connecting the turns in aplanar-parallel manner to form the spiral reduces the conductor's seriesresistance, thereby giving a higher Q factor. However, the inductanceproduced is very low compared to the conventional design. Therefore, theinductive behavior of such parallel inductors is expected by thoseskilled in the art to be unsatisfactory and this as been found to be thecase.

[0014] Solutions to these problems have been long sought, but have longeluded those skilled in the art.

DISCLOSURE OF THE INVENTION

[0015] A parallel spiral stacked inductor and manufacturing methodtherefore is provided. A substrate has a plurality of turns in aplurality of levels, the plurality of turns having a center proximateand a center distal ends. A first plurality of vias connecting thecenter proximate ends of the plurality of turns and a second pluralityof vias connecting the center distal ends of the plurality of turns. Afirst connecting portion connects to the center proximate ends of theplurality of turns and a second connecting portion connecting to thecenter distal end of the plurality of turns. A dielectric materialcontains the inductor.

[0016] The present invention provides a stacked parallel inductorwherein the performance is comparable if not better than theconventional stacked inductor. Despite achieving low inductance whenmetal strips are laid out in a parallel manner, Q factor of the inductorimproves by a significant 30%. Hence, if metal strips can be connectedin a parallel manner without affecting the overall inductance, suchparallel inductors show tremendous potential in replacing theconventional stacked spiral inductors.

[0017] The present invention further provides an alternative, if notbetter solution, to replace the conventional stacked spiral inductor.The planar parallel inductor yields unsatisfactory results. Its lowinductance can be overcome in the stacked parallel design. The layout ofthe parallel spiral conductors allows performance of parallel inductorsto be comparable to conventional stacked inductors. The inductor of thepresent invention is achieved when vias along conductors of theconventional stacked inductor are removed. This means only the regionsat the two ends of the metal layers making up the main spiral areconnected with vias. It has been found that even though conductors areelectrically connected in parallel, the inductance value is not reducedas in the case of a planar parallel inductor. The stacked parallelinductor has a much higher inductance value compared to the parallelinductor because of the presence of mutual coupling between adjacentconductors. Since the conductors are stacked on top of each other, thelarge conductor surface areas as well as the thin inter metal dielectricpromote a significant constructive mutual coupling effect. Hence, mutualinductance generated through this strong coupling compensates for thereduction in self-inductance of the metal lines when they are connectedin a parallel fashion. The Q factor for the new design is observed to beslightly higher than the conventional stacked inductor at allfrequencies.

[0018] The above and additional advantages of the present invention willbecome apparent to those skilled in the art from a reading of thefollowing detailed description when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 (PRIOR ART) is a cross-sectional view of a prior arton-chip inductor along line 1-1 of FIG. 2 (PRIOR ART);

[0020]FIG. 2 (PRIOR ART) is a cross-sectional view of the prior arton-chip inductor along line 2-2 of FIG. 1 (PRIOR ART);

[0021]FIG. 3 is shown a cross-sectional view of a parallel spiralstacked inductor of the present invention along line 3-3 of FIG. 4; and

[0022]FIG. 4 is shown a cross-sectional view of the parallel spiralstacked inductor of the present invention along line 4-4 of FIG. 3.

BEST MODE FOR CARRYING OUT THE INVENTION

[0023] Referring now to FIG. 1 (PRIOR ART), therein is shown across-sectional view of a prior art on-chip inductor 10 along line 1-1of FIG. 2 (PRIOR ART). A substrate 12, of a material such as silicon,has a plurality of dielectric layers formed thereon of a material suchas silicon dioxide. Sequentially, a field dielectric layer 14 (such as afield oxide), a connecting interlayer dielectric (ILD) layer 16 (such asa silicon oxide), a first level ILD layer 18, and a second level ILDlayer 20 are formed over the substrate 12. Embedded within thedielectric layers is a spiral stacked inductor 22.

[0024] The term “over” as used in herein is defined vertically above ahorizontal plane parallel to the conventional surface of a wafer onwhich the on-chip inductor is formed regardless of the orientation ofthe wafer. Terms, such as “on”, “below”, “higher”, “lower”, “above”, and“under”, are defined with respect to the horizontal plane.

[0025] The term “processed” or “forming” as used herein to refer to theformation of vias and turns includes conventional semiconductordeposition of photoresist, hard and soft mask photolithography, etch,and strip, as appropriate.

[0026] In the prior art, the spiral stacked inductor 22 is a two-turnstacked inductor. In FIG. 1 (PRIOR ART), are shown first and secondturns 24 and 26.

[0027] A first connecting portion 30 having connecting vias 32 connectsto the spiral stacked inductor 22 at one end and a second connectingportion 34 connects at the other end.

[0028] The first turn 24 has an inner diameter 36, a width 38 which iscommon to each of the turns, and a spacing 40 between each of the turns.The first connecting portion 30 passes under the two turns and thus isalso referred to as an underpass 30.

[0029] Referring now to FIG. 2 (PRIOR ART), therein is shown across-sectional view of the prior art on-chip inductor 10 along line 2-2of FIG. 1 (PRIOR ART). The substrate 12 has the field dielectric layer14 upon which a conductive material is deposited and patterned to formthe underpass 30.

[0030] The connecting ILD layer 16 is then deposited over the underpass30. One or more first via openings are formed in the connecting ILDlayer 16 connected to the underpass 30.

[0031] A conductive material layer is deposited on the connecting ILDlayer 16 and processed to form a first level of the spiral stackedinductor 22. When processed, first and second turns 24′ and 26′ of afirst level 50′ will be formed. The first via openings are also filledwith conductive material to form connecting vias 32.

[0032] The first level ILD layer 18 is then deposited over the firstlevel 50′. One or more second via openings are formed in the first levelILD layer 18 connected to the first and second turns 24′ and 26′ alongtheir lengths.

[0033] A conductive material is deposited on the first level ILD layer18 and processed to form the first and second turns 24 and 26 of asecond level 50′. The first and second turns 24 and 26 are respectivelyconnected to the first and second turn vias 24 v and 26 v along theirlengths by the conductive material filling the respective vias openingsto form first and second turn vias 24 v and 26 v.

[0034] The second level ILD layer 20 is then deposited over the secondlevel 50′.

[0035] As will be understood by those skilled in the art, as a spiralstacked inductor has more turns, it will still have the same number ofturns in each level and the turns will all be connected along theirlength by pluralities of vias.

[0036] Referring now to FIG. 3, therein is shown a cross-sectional viewof a parallel spiral stacked on-chip inductor 100 of the presentinvention along line 3-3 of FIG. 4. A substrate 112, of a material suchas silicon, has a plurality of dielectric layers formed thereon of amaterial such as silicon dioxide. Sequentially, a field dielectric layer114 (such as a field oxide), a connecting interlayer dielectric (ILD)layer 116 (such as a silicon oxide), a first level ILD layer 118, asecond level ILD layer 120, and a third level ILD layer 121 are formedover the substrate 112. Embedded within the dielectric layers is aparallel spiral stacked inductor 122.

[0037] The parallel spiral stacked inductor 122 is shown as being squarespiral but it may also be circular spiral. Similarly, the parallelspiral stacked inductor 122 can be a spiral, which is either clockwiseor counter clockwise as viewed from above.

[0038] In the described embodiment, the parallel spiral stacked inductor122 is a parallel two-turn inductor. In FIG. 3, are shown first andsecond turns 124 and 126. Individually, the turns can be flat as shownor circular, and can be made from any conductive material includingcopper.

[0039] A first connecting portion 130 having connecting vias 132connects to the parallel spiral stacked inductor 122 at one end and asecond connecting portion 134 having connecting vias 133 connects at theother end.

[0040] The first turn 126 has an inner diameter 136, a width 138 whichis common to each of the turns, and a spacing 140 between each of theturns. The first connecting portion 130 passes under the two turns andthus is also referred to as an underpass 130.

[0041] Referring now to FIG. 4, therein is shown a cross-sectional viewof the parallel spiral stacked inductor 100 of the present inventionalong line 4-4 of FIG. 3. The substrate 112 has the field dielectric 114upon which a conductive material is deposited and patterned to form theunderpass 130.

[0042] The connecting ILD layer 116 is then deposited over the underpass130. One or more first via openings are formed in the connecting ILDlayer 116 connected to the underpass 130.

[0043] A conductive material layer is deposited on the connecting ILDlayer 116 and processed to form a first level of the parallel spiralstacked inductor 122. When processed, first and second turns 124′ and126′ of a first level 150′ will be formed.

[0044] The first level ILD layer 118 is then deposited over the firstlevel 150′. One or more second via openings formed in the first levelILD layer 118 connected to the center proximate end of the first turn124′ and to the center distal end of the first turn 124′.

[0045] A conductive material is deposited on the first level ILD layer118 and processed to form the first and second turns 124 and 126 and thesecond connecting portion 134 of a second level 150′. The first andsecond turns 124 and 126 are respectively connected to the first andsecond turns 124′ and 126′ at their center proximate and center distalends only by the conductive material filling the second via openings toform center proximate and center distal end vias 132 v and 133,respectively.

[0046] The second level ILD layer 120 is then deposited over the secondlevel 150′.

[0047] As will be understood by those skilled in the art, as the spiralstacked inductor 22 has more turns, it will still have the same numberof turns in each level and the turns will all be connected bypluralities of vias. On the other hand, as the parallel spiral stackedinductor 122 has more turns, each level of spiral of turns will be onlyconnected at the center proximate and center distal ends.

[0048] Also as will be understood by those skilled in the art, parallelcircular stacked inductors could be made in the same fashion as shownwith various diameters, widths, and spacings. Similarly, differentmetals can be used for the inductors including aluminum and copper.

[0049] While the invention has been described in conjunction with aspecific best mode, it is to be understood that many alternatives,modifications, and variations will be apparent to those skilled in theart in light of the aforegoing description. Accordingly, it is intendedto embrace all such alternatives, modifications, and variations thatfall within the spirit and scope of the included claims. All mattershither-to-fore set forth or shown in the accompanying drawings are to beinterpreted in an illustrative and non-limiting sense.

The invention claimed is:
 1. A method of manufacturing a parallelstacked inductor comprising: providing a substrate; forming a firstconductive material layer over the substrate; processing the firstconductive material layer to form a first turn; forming a firstdielectric layer over the substrate and the first turn; forming firstand second via openings in the first dielectric layer connected to onlyto distal ends of the first turn; forming a second conductive materiallayer over the first dielectric layer and in the first and second viaopenings; processing the second conductive material layer to form asecond turn connected only to the distal ends of the first turn by thesecond conductive material in the first and second via openings formingfirst and second vias therebetween; and forming a second dielectriclayer over the first dielectric layer and the second turn.
 2. The methodas claimed in claim 1 including: forming third and fourth via openingsin the second dielectric layer connected to only to distal ends of thesecond turn; forming a third conductive material layer over the seconddielectric layer and in the third and fourth via openings; processingthe third conductive material layer to form a third turn connected onlyto the distal ends of the second turn by the third conductive materialin the third and fourth via openings forming third and fourth viastherebetween; and forming a third dielectric layer over the seconddielectric layer and the third turn.
 3. The method as claimed in claim 1including: forming a first connecting portion under the first turn andconnected to one of the distal ends of the first turn.
 4. The method asclaimed in claim 3 including: forming a second connecting portion whileprocessing a conductive material layer selected from the groupconsisting of the second conductive material layer, the third conductivematerial layer, and a combination thereof.
 5. A method of manufacturinga parallel spiral stacked inductor comprising: providing a substrate;forming a first conductive material layer over the substrate; processingthe first conductive material layer to form a first plurality of turns,the first plurality of turns having a center proximate and a centerdistal ends; forming a first dielectric layer over the substrate and thefirst plurality of turns; forming first and second via openings in thefirst dielectric layer respectively connected to only to the centerproximate and center distal ends of the first plurality of turns;forming a second conductive material layer over the first dielectriclayer and in the first and second via openings; processing the secondconductive material layer to form a second plurality of turns connectedonly to the center proximate and center distal ends of the firstplurality of turns by the second conductive material in the first andsecond via openings forming first and second vias therebetween; andforming a second dielectric layer over the first dielectric layer andthe second plurality of turns.
 6. The method as claimed in claim 5including: forming third and fourth via openings in the seconddielectric layer connected to only to the center proximate and centerdistal ends of the second plurality of turns; forming a third conductivematerial layer over the second dielectric layer and in the third andfourth via openings; processing the third conductive material layer toform a third plurality of turns connected only to the center proximateand center distal ends of the second plurality of turns by the thirdconductive material in the third and fourth via openings forming thirdand fourth vias therebetween; and forming a third dielectric layer overthe second dielectric layer and the third plurality of turns.
 7. Themethod as claimed in claim 5 including: forming a field dielectric layerover the substrate; forming a connecting conductive material layer overthe field dielectric layer; processing the second conductive materiallayer to form a connecting portion, the connecting portion having acenter proximate end; forming a connecting dielectric layer over thefield dielectric layer and the connecting portion; and forming aconnecting via opening in the field dielectric layer connected to thecenter proximate end of the connecting portion; and wherein: processingthe first conductive material layer connects the center proximate endsof the connecting portion and the first plurality of turns.
 8. Themethod as claimed in claim 7 including: forming a second connectingportion while processing a conductive material layer selected from thegroup consisting of the first conductive layer, the second conductivematerial layer, the third conductive material layer, and a combinationthereof.
 9. A parallel stacked inductor comprising: a substrate; aplurality of turns in a plurality of levels, the plurality of turnshaving distal ends; a plurality of vias connecting the distal ends ofthe plurality of turns; a first connecting portion connected to one ofthe distal ends of the plurality of turns in the level proximate thesubstrate; a second connecting portion connected to the other of thedistal ends of the plurality of turns; and a dielectric materialcontaining the first and second connecting portions and the plurality ofturns.
 10. A parallel spiral stacked inductor comprising: a substrate; aplurality of turns in a plurality of levels, the plurality of turnshaving a center proximate and a center distal ends; a first plurality ofvias connecting the center proximate ends of the plurality of turns; asecond plurality of vias connecting the center distal ends of theplurality of turns; a first connecting portion connected to the centerproximate ends of the plurality of turns; a second connecting portionconnected to the center distal end of the plurality of turns; and adielectric material containing the first and second connecting portions,the plurality of turns, and the first and second plurality of vias. 11.A parallel stacked inductor comprising: a substrate; a first turn ofconductive material over the substrate; a first dielectric layer overthe substrate and the first turn; a second turn of conductive materialover the first dielectric layer; first and second vias of conductivematerial connected only to the distal ends of the first turn; and asecond dielectric layer over the first dielectric layer and the secondturn.
 12. The inductor as claimed in claim 11 including: third andfourth vias of conductive material connected only to distal ends of thesecond turn; a third turn of conductive material over the seconddielectric layer connected only to the distal ends of the second turn bythe third and fourth vias; and a third dielectric layer over the seconddielectric layer and the third turn.
 13. The inductor as claimed inclaim 11 including: a first connecting portion under the first turn andconnected to one of the distal ends of the first turn.
 14. The inductoras claimed in claim 13 including: a second connecting portion ofconductive material layer connected to a turn selected from the groupconsisting of the first turn, the second turn, the third turn, and acombination thereof.
 15. A parallel spiral stacked inductor comprising:a substrate; a first plurality of turns of conductive material over thesubstrate, the first plurality of turns having a center proximate and acenter distal ends; a first dielectric layer over the substrate and thefirst plurality of turns; a second plurality of turns of conductivematerial over the first dielectric layer; first and second vias ofconductive material respectively connected only to the center proximateand the center distal ends of the first plurality of turns; and a seconddielectric layer over the first dielectric layer and the secondplurality of turns.
 16. The inductor as claimed in claim 15 including:third and fourth vias of conductive material respectively connected onlyto he center proximate and the center distal ends of the secondplurality of turns; a third plurality of turns of conductive materialover the second dielectric layer connected only to the distal ends ofthe center distal ends of the second plurality of turns by the third andfourth vias; and a third dielectric layer over the second dielectriclayer and the third plurality of turns.
 17. The inductor as claimed inclaim 15 including: a first connecting portion under the first pluralityof turns and connected to the center proximate end of the firstplurality of turns.
 18. The inductor as claimed in claim 17 including: asecond connecting portion of conductive material layer connected to aturn selected from the group consisting of the first plurality of turns,the second plurality of turns, the third plurality of turns, and acombination thereof.